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Survey Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014
1324 - 1330A Survey on Analytical Delay Models for CMOS Inverter-Transmission Gate Structure
Sreelakshmi V. | Dr. K. Gnana Sheela
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Survey Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014
659 - 666A Survey on Buffered Clock Tree Synthesis for Skew Optimization
Anju Rose Tom | K. Gnana Sheela [2]
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